555 Timer: Pinout, How It Works and Astable Circuit

What the 555 timer is

The 555 is a timer on a chip. Hans Camenzind designed it at Signetics in 1971, by hand and breadboard rather than computer simulation, and IEEE Spectrum later counted it among the microchips that shook the world. The original die held 23 transistors, 16 resistors and 2 diodes, and NXP, which inherited Signetics, puts sales in the many billions. More than fifty years on, Texas Instruments, Renesas, Diodes Incorporated and others still make it, in the original bipolar form (NE555, SA555, SE555, LM555) and in low-power CMOS versions (TLC555, LMC555, ICM7555). Dual versions such as Renesas’s ICM7556 put two timers in one package.

What makes it useful is that the timing depends on a resistor and a capacitor, not on the supply voltage. Both switching thresholds are fixed fractions of the supply, and the capacitor charges at a rate that is also proportional to the supply, so the two cancel. The same chip times anything from microseconds to hours, drives an LED or a relay straight from its output, and in its bipolar form takes any supply from 4.5 V to 16 V.

555 pinout

The 555 in an 8-pin DIP or SOIC package, seen from above. Pin 1 is beside the notch or dot, and numbering runs counter-clockwise, so pin 8 sits opposite pin 1.

The pin numbers are the same in the 8-pin DIP and SOIC packages and in TI’s other 8-pin versions; the 20-pin LCCC package numbers its pins differently, so check the datasheet for anything else. What each pin does, and how it is usually connected:

Pin	Name	What it does	Usual connection
1	GND	Ground reference for everything else.	0 V
2	TRIG	Starts a timing cycle: below ⅓ VCC (half the CONT voltage) it sets the output high and turns the discharge transistor off.	The timing capacitor (astable) or an input held high by a pull-up (monostable)
3	OUT	The output: close to VCC when high, close to 0 V when low.	The load, a logic input or a transistor base
4	RESET	Active low. Pulled low, it forces the output low and the discharge transistor on, overriding every other input.	VCC when unused
5	CONT	The ⅔ VCC point of the internal divider. Driving it moves both thresholds.	10 nF to ground, or a control voltage
6	THRES	Ends a timing cycle: above ⅔ VCC (the CONT voltage) it sets the output low and turns the discharge transistor on.	The timing capacitor
7	DISCH	An open-collector transistor to ground, on whenever the output is low.	Between the timing resistors, or across the capacitor
8	VCC	Supply.	4.5–16 V for the NE555, decoupled at the pin

Inside the 555: how it works

The functional blocks of a 555. In the bipolar NE555 and LM555 each divider resistor is 5 kΩ; in Renesas’s CMOS ICM7555 each is about 100 kΩ.

Three equal resistors in series across the supply make two reference voltages: ⅔ VCC at the upper junction, which is also brought out to pin 5, and ⅓ VCC at the lower one. Two comparators watch the inputs. The threshold comparator trips when pin 6 rises above ⅔ VCC and resets the latch; the trigger comparator trips when pin 2 falls below ⅓ VCC and sets it. The latch remembers which happened last. Its output drives the output stage on pin 3 and, inverted, the base of the discharge transistor, whose collector is pin 7: with the output low, pin 7 is shorted to ground; with the output high, pin 7 is open.

When inputs conflict, TI’s function table settles them in a fixed order: RESET overrides TRIG, which overrides THRES. With RESET low the output is low, whatever else happens. With RESET high, a trigger below ⅓ VCC holds the output high even if the threshold is also above ⅔ VCC. Only when neither comparator has tripped does the latch simply hold its last state. Every circuit below follows from those rules.

Nominal switching levels with pin 5 left to the internal divider.
Supply	5 V	9 V	12 V	15 V
Trigger level, ⅓ VCC (pin 2)	1.67 V	3 V	4 V	5 V
Threshold level, ⅔ VCC (pins 5 and 6)	3.33 V	6 V	8 V	10 V

Pin 5 is where the design opens up. Both thresholds come from the divider, so driving pin 5 to another voltage moves both: the trigger level is always half the CONT voltage. In an astable on a 9 V supply, pulling pin 5 down to 4.5 V shortens the high time to 58 % of normal, and pushing it up to 7 V stretches it to 146 %; the low time, a halving from CONT to half of CONT, does not change. That is how a 555 becomes a pulse-width or pulse-position modulator, both circuits in TI’s datasheet, or a simple voltage-controlled oscillator. When the pin is not used, a 10 nF capacitor to ground keeps noise off the thresholds.

555 astable circuit: the free-running oscillator

The 555 astable circuit, here flashing an LED. Pins 2 and 6 are joined at the capacitor; pin 7 sits between R1 and R2.

In astable mode the 555 triggers itself. R1 runs from the supply to pin 7, R2 from pin 7 to the capacitor, and the top of the capacitor connects to both pin 6 and pin 2. With the output high and pin 7 open, C charges through R1 and R2 in series. When it reaches ⅔ VCC the threshold comparator resets the latch: the output goes low and pin 7 shorts the junction of R1 and R2 to ground, so C discharges through R2 alone. At ⅓ VCC the trigger comparator sets the latch again, pin 7 lets go, and the cycle repeats.

Astable waveforms drawn to scale for R1 = 22 kΩ, R2 = 10 kΩ and C = 10 µF. The capacitor swings between ⅓ and ⅔ of the supply; the very first charge starts from 0 V and takes longer.

Because the capacitor always swings between the same two fractions of the supply, the high time, low time and frequency are:

t_{H} = \ln (2) \cdot (R_{1} + R_{2}) \cdot C

t_{L} = \ln (2) \cdot R_{2} \cdot C

f = \frac{1}{\ln (2) \cdot (R_{1} + 2 \cdot R_{2}) \cdot C} \approx \frac{1.44}{(R_{1} + 2 \cdot R_{2}) \cdot C}

For the waveform above, tH = 222 ms and tL = 69.3 ms, so the circuit runs at 3.43 Hz with a duty cycle of 76.2 %. The first high period is 352 ms, because the capacitor starts from 0 V rather than ⅓ VCC. To watch it run, open the 555 astable in the circuit simulator.

555 monostable circuit: the one-shot timer

The 555 monostable: the timing resistor and capacitor on pins 6 and 7, and a push button that pulls the trigger, pin 2, low against a pull-up.

In monostable mode the 555 waits with its output low and pin 7 holding the capacitor discharged. A falling pulse on pin 2, below ⅓ VCC, sets the latch: the output goes high, pin 7 releases C, and C charges through R from 0 V. At ⅔ VCC the threshold comparator resets the latch, the output drops and pin 7 empties C, ready for the next trigger. The output pulse lasts:

t = \ln (3) \cdot R \cdot C \approx 1.1 \cdot R \cdot C

TI’s LM555 datasheet builds this circuit with R = 100 kΩ and C = 47 µF. The formula gives 5.163 s, and TI reports about 5.17 s. Design around three behaviours:

The trigger must end before the pulse does. Because TRIG overrides THRES, holding pin 2 low keeps the output high for as long as it is held. For a push button or a long input, couple the trigger through a small capacitor with a pull-up, so only the falling edge counts.
It does not retrigger. Trigger pulses that arrive during the timing period are ignored. TI uses this as a frequency divider: make the period a little longer than two input periods and the output marks every third input pulse.
Restart with RESET. Pulling RESET and TRIG low together discharges C and starts a fresh period when RESET is released.

There is a floor too. TI puts the NE555’s shortest reliable pulse at about 10 µs, set by its comparator storage time; the CMOS TLC555 manages about 1 µs. Try the 555 monostable in the simulator.

Bistable mode: a set–reset latch

The 555 as a bistable latch: SET pulls the trigger low, RESET pulls the reset pin low, the threshold is grounded and there are no timing parts.

Leave out the timing parts and the 555 becomes a set–reset latch with a strong output. TRIG and RESET are each held high by a pull-up resistor (TI suggests about 10 kΩ on RESET for the TLC555) and pulled low by a push button. THRES goes to ground so the threshold comparator never fires, and DISCH is left open, or used as a second, open-collector output that pulls low whenever OUT is low.

Press SET: TRIG falls below ⅓ VCC, the latch sets, and the output goes high and stays high after the button is released. Press RESET: the output goes low and stays low. Press both and the output is low, because RESET overrides TRIG. It is the function table with the timing taken out, and it makes a cheap push-button on/off control, a fault latch that holds a trip until someone resets it, or a bounce-free flip-flop that can drive a relay coil. A related trick joins pins 2 and 6 as a single input, turning the 555 into an inverting Schmitt trigger that switches at ⅔ VCC going up and ⅓ VCC going down.

Calculate 555 timer values

The calculator works the formulas in both directions: astable frequency and duty cycle from R1, R2 and C; monostable pulse width from R and C; or, in design mode, R1 and R2 for a target frequency and duty cycle with the capacitor you have, rounded to E12 or E24 values and with a diode’s drop included if you use one. The full 555 timer calculator adds frequency and pulse-width tables and worked designs.

Result

f = 6.87 Hz · duty 52.4 %

R1 = 1 kΩ, R2 = 10 kΩ and C = 10 µF oscillate at 6.87 Hz (period 146 ms): high for 76.2 ms, low for 69.3 ms, a 52.4 % duty cycle.

Frequency: 6.87 Hz
Period: 145.6 ms
High time (tH): 76.25 ms
Low time (tL): 69.31 ms
Duty cycle (high): 52.38 %
1.44 / ((R1 + 2R2)C): 6.857 Hz

Show the work

1. High time: C charges through R1 + R2
$t_{H} = \ln (2) \cdot (R_{1} + R_{2}) \cdot C = 0.6931 \cdot (1 kΩ + 10 kΩ) \cdot 10 µF = 76.25 ms$
2. Low time: C discharges through R2 into pin 7
$t_{L} = \ln (2) \cdot R_{2} \cdot C = 0.6931 \cdot 10 kΩ \cdot 10 µF = 69.31 ms$
3. Frequency
$f = \frac{1}{t_{H} + t_{L}} = \frac{1}{76.25 ms + 69.31 ms} = 6.87 Hz$
Datasheet shortcut: f ≈ 1.44 / ((R1 + 2R2)·C) = 6.857 Hz. The 1.44 is 1/ln 2 = 1.4427 rounded, so the shortcut reads 0.19 % low.
4. Duty cycle: share of each period the output is high
$D = \frac{R_{1} + R_{2}}{R_{1} + 2 \cdot R_{2}} = \frac{1 kΩ + 10 kΩ}{1 kΩ + 2 \cdot 10 kΩ} = 52.38 %$

References: TI NE555 datasheet (SLFS022K) (rev. March 2026): astable tH, tL and frequency (eq. 1–4), monostable tw ≈ 1.1RC, RA + RB limits, 100 kHz guidance

Duty cycle is the fraction of each period the output (pin 3) is high. The very first high period after power-up is longer, because C starts from 0 V instead of ⅓ of the supply.
Thresholds at ⅓ and ⅔ of the supply: the control pin (5) is not driven; a 10 nF capacitor from it to ground is fine.
Timing parts at their nominal values. Electrolytic capacitors are often ±20 %, and that usually dominates the real error.
Propagation delays and the discharge transistor’s on-resistance are ignored; they start to matter above about 100 kHz.

555 timing formulas: ln 2, ln 3 and the 1.44 shortcut

Every 555 time comes from one equation. A capacitor charging through a resistor towards a voltage V∞ closes the gap exponentially, so the time to go from V₀ to V₁ is:

t = R \cdot C \cdot \ln (\frac{V_{\infty} - V_{0}}{V_{\infty} - V_{1}})

Charging from ⅓ to ⅔ of the supply, towards the supply: the gap goes from ⅔ to ⅓, a factor of 2, so t = RC ln 2.
Discharging from ⅔ to ⅓, towards 0 V: the gap halves again, so t = RC ln 2.
Charging from 0 to ⅔ (the monostable, and the first astable cycle): the gap falls from the whole supply to a third, so t = RC ln 3.

The supply voltage cancels out of every ratio, which is where the 555’s supply independence comes from. Datasheets round the constants: 1/ln 2 = 1.4427 becomes 1.44, which reads 0.19 % low, and ln 3 = 1.0986 becomes 1.1, which reads 0.13 % long. Both errors are far inside the tolerance of any timing capacitor, so the shortcuts are fine for design; the calculator uses the exact constants anyway.

Duty cycle limits and the diode trick

The output is high while C charges through R1 + R2 and low while it discharges through R2 alone, so the duty cycle is:

D = \frac{R_{1} + R_{2}}{R_{1} + 2 \cdot R_{2}}

That is always above 50 %. With R1 at its practical minimum of 1 kΩ (smaller, and too much current flows into pin 7 every time it discharges) and R2 a hundred times larger, the duty cycle is 50.25 %; swap the two and it is 99.02 %. Three ways to get below 50 %:

A diode across R2, anode at pin 7. C then charges through R1 and the diode and discharges through R2, so the duty cycle is roughly R1 ÷ (R1 + R2), and equal resistors give about 50 %. The diode’s forward voltage slows the charge, though. Working it through the RC equation (our own derivation; no 555 datasheet gives it), a silicon diode lengthens the high time by 44.6 % on a 5 V supply and 11.3 % on 15 V. The calculator’s diode option includes that correction.
Invert the output. The low time is the short one, so a transistor or logic inverter after pin 3 turns a 70 % waveform into a 30 % one.
On CMOS parts, feed the output back. Renesas shows a single resistor from pin 3 to pins 2 and 6, with C to ground. Because a CMOS output swings from rail to rail, charge and discharge are symmetrical and the duty cycle is 50 %, with f ≈ 1 ÷ (1.4RC). That circuit comes from Renesas alone; the same RC algebra gives the exact constant, 2 ln 2 = 1.386, so R = 10 kΩ and C = 100 nF run at 721 Hz (Renesas’s rounding gives 714 Hz).

The astable with a diode across R2: the capacitor charges through R1 and D, and discharges through R2 into pin 7, so the high time no longer includes R2.

Bipolar NE555 vs CMOS TLC555, LMC555 and ICM7555

Datasheet figures (TI SLFS022K, SLFS043K, SNAS558N; Renesas FN2867).
Figure	NE555 (bipolar)	TLC555 (CMOS)	LMC555 (CMOS)	ICM7555 (CMOS)
Supply range	4.5–16 V	2–15 V	1.5–15 V	2–18 V
Supply current	3 mA typ (6 max) at 5 V	180 µA typ (350 µA max) at 5 V	180 µA at 5 V	low (µA range)
Highest astable frequency	100 kHz or less recommended	2.1 MHz typical	3 MHz typical	1 MHz
Largest total timing resistance	about 3.4 MΩ at 5 V, 10 MΩ at 15 V	no datasheet limit: input currents are picoamps, so capacitor and board leakage set it

The bipolar NE555 is the rugged original. TI rates its output at up to 200 mA, sinking or sourcing, so it drives relays and LEDs directly, and it forgives sloppy layout. But it draws milliamps even when idle, needs at least 4.5 V, and each time its output switches, the output stage briefly conducts from supply to ground. Renesas calls these crowbar currents; they can retrigger the timer or upset nearby logic, which is why TI asks for a 0.1 µF ceramic capacitor right at pin 8 as well as the 10 nF on pin 5. Its threshold input also draws up to 250 nA (30 nA typical), which is what limits the timing resistance.

The CMOS versions fix most of that. Their inputs draw picoamps, so timing resistors of many megohms work; they start from as little as 1.5 V (LMC555) or 2 V (TLC555, ICM7555); they draw a few hundred microamps at most; and Renesas measures switching spikes of a few milliamps on its ICM7555 against hundreds of milliamps for a bipolar 555. The price is output drive: TI specifies the TLC555 at about 100 mA sinking but only about 10 mA sourcing, so a relay or LED string needs a transistor. The pinout is identical, so most circuits accept either part.

How fast can a 555 run?

TI recommends keeping the NE555 at 100 kHz or below and suggests the TLC555 for anything faster. The reason is that the formulas assume the comparators, latch and discharge transistor switch instantly. They don’t. Each half-cycle runs on for the propagation delay, so the capacitor overshoots the threshold, and the discharge transistor’s on-resistance adds to R2. At low frequencies those errors are a tiny part of the period; at high frequencies they dominate.

TI’s own TLC555 data shows how far off the formula gets. The maximum-frequency test circuit uses RA = 470 Ω, RB = 200 Ω and C = 200 pF. The textbook formula predicts 8.29 MHz for those parts; the TLC555 typically reaches 2.1 MHz, about 3.9 times slower than predicted. TI gives corrected equations for use above 100 kHz that add the delay times and the discharge resistance, and in them the ln 2 term drifts towards ln 3 as the delays become comparable with the time constant.

In practice: above about 100 kHz use a CMOS part and expect to trim; keep the timing capacitor above roughly 100 pF so that a few picofarads of pin and board capacitance do not swamp it (our rule of thumb, not a datasheet limit); and for crystal accuracy or tens of megahertz, use an oscillator or a microcontroller timer instead.

Common 555 applications

Flashers and blinkers: an astable driving an LED through a series resistor; size the LED resistor from the output’s high voltage.
Tone and alarm generators: an astable in the audio range driving a piezo sounder or a small speaker through a capacitor.
Delay-on and delay-off timers: a monostable switching a relay, with a diode across the coil, for fans, lights or pumps that run on after a signal.
Debouncing and pulse stretching: a monostable turns a bouncing switch or a short glitch into one clean pulse of known length.
Missing-pulse detectors: a monostable kept from timing out by a steady pulse train, so a missing pulse, from a stalled fan or a stopped conveyor, produces an output. TI shows this circuit; simulate it.
Pulse-width and pulse-position modulation: a signal on pin 5 varies the pulse length or position, for dimmers, simple motor speed control and modulation (simulate PWM).
Sequential timers and frequency dividers: chained monostables step through a sequence, and a monostable that ignores some triggers divides a frequency.
Infrared carriers: a 38 kHz astable at about 50 % duty for IR remote receivers; the calculator’s design mode works one out with a diode.

Troubleshooting a 555 circuit

Symptom	Likely cause	Fix
Output stuck low, nothing happens	RESET (pin 4) floating or pulled low	Tie pin 4 to VCC, or pull it up if logic drives it
Monostable output stuck high	TRIG held below ⅓ VCC for longer than the pulse	Shorten the trigger: couple it through a small capacitor with a pull-up
Frequency or delay well off the formula	Capacitor tolerance or leakage; a diode’s drop; reading the longer first cycle	Measure C and use a film capacitor; include the diode drop; time later cycles
Long delays never end	Electrolytic leakage rivals the tiny charging current through megohm resistors	Use a smaller resistor with a larger film capacitor, or a 555 driving a counter
Won’t run on a 3.3 V supply	The bipolar NE555 needs at least 4.5 V	Use a CMOS part: TLC555 from 2 V, LMC555 from 1.5 V
Random retriggering, or nearby logic glitches	Supply spikes from the bipolar output stage	0.1 µF ceramic at pin 8, 10 nF on pin 5, short ground returns; or a CMOS part
Chip runs hot or fails	R1 too small: pin 7 shorts the supply through R1 at every discharge	Keep R1 at 1 kΩ or more and scale C instead
Fails after driving a relay	No diode across the coil	Add a flyback diode across the relay coil
CMOS 555 can’t light an LED string	CMOS outputs source only milliamps	Drive the load through a transistor
Frequency drifts with temperature	A high-capacitance ceramic (X7R, Y5V) as the timing capacitor	Use C0G/NP0 or film for timing

To see the inside of the chip at work, open the simulator’s 555 internals circuit, which shows the divider, comparators and latch switching in real time. Check the timing parts themselves with the resistor colour code calculator, and if pin 5 is driven from a fixed voltage, calculate the divider that sets it.

555 timer